It is desired to integrate increasing numbers of high-performance capacitors, in terms of linearity and leakage current, into microelectronic devices such as RF circuits or “systems on a chip” (SoC). It is also desired to optimize the capacitance per unit area of these devices. To satisfy these requirements, three-dimensional capacitors have appeared. These capacitors are equipped with “horizontal” armature or electrode parts, meaning that they are parallel to the principal plane of a substrate, and “vertical” armature or electrode parts, meaning that they are making a nonzero angle with the principal plane of the substrate or are orthogonal to the principal plane of the substrate. These capacitors are generally formed by at least one step of a method of the Damascene type, by the filling of slots with an MIM stack including a thin metal layer, a thin insulating layer and another thin metal layer.
In FIG. 1, a microelectronic device equipped with at least one three-dimensional metal-insulation-metal (MIM) capacitor, known as a “3D MIM” is illustrated. This device is equipped with at least one three-dimensional capacitor arranged to satisfy the requirements of small size and large capacitance simultaneously. The device is formed from a substrate 1 on which, for example, a plurality of components and of superimposed metal interconnection levels, such as 6 metal interconnection levels M1, M2, M3, M4, M5, M6, have been created (the components and the first four metal interconnection levels M1, . . . , M4 being shown in FIG. 1 by a block in broken lines above the substrate 1).
In this device, the capacitor 2 is equipped with armatures formed from “vertical” metal parts created in a plane that is orthogonal to the principal plane of the substrate 1, from a first thin metal layer 3, and from a second thin metal layer 5 separated from the first thin metal layer 3 by a thin dielectric material layer 4. The thin dielectric layer 4 and the second thin metal layer 5 cover the walls and the bottom of slots created in an insulating layer 6 in which are formed metal connection elements 7, commonly called “vias”, between the fifth metal level M5 and the sixth metal level M6. The armatures of the capacitor also include horizontal metal parts 8 and 9 formed in metal layers of the fifth metal level M5 and of the sixth metal level M6 respectively.
Creation of the lower structure of such a capacitor, and in particular of the horizontal metal part 8 of this capacitor in the metal layer of the fifth metal level M5 gives rise to a problem. The metal material on the basis of which the metal part 8 is created is generally copper. The copper induces stresses that have a tendency to result, during steps executed after the deposition of this metal and requiring a high thermal input, in the formation of protuberances or “hillocks” on the surface of this copper metal part 8.
These protuberances have a tendency to give rise to manufacturing faults in the parts of the device located above the fifth metal level, and to damage the electrical performance of the capacitor 2, in particular in terms of breakdown voltage. The faults engendered also increase as the area allocated to the metal part 8 increases.
In FIG. 2, the curves C1 and C2 are examples of break-down voltage curves, respectively when the metal part 8 of the lower structure of the capacitor 2 has an area of the order of 5,000 μm2 for example, and when this metal part 8 has an area of the order of 50,000 μm2 for example. The reduction in the electrical performance of the capacitor 2, in terms of breakdown voltage, increases as the area of the metal part 8 increases.
One approach used to address the breakdown voltage of the capacitor 2 is therefore to reduce the area of the metal part 8 of its lower structure, for example by giving this metal part 8, in a plane parallel to the principal plane of the substrate, a shape or a design according to the shape or the design created by the filled slots of the MIM stack located in another plane parallel to the principal plane of the substrate. As an example, in the case in which the filled slots of the MIM stack create a comb-shaped pattern, the metal part 8 can also be designed with this same comb-shaped pattern. However, such an approach results in reducing the capacitor surface capacitance Co, to the extent that a minimum space is imposed between the teeth of the comb, by the lower metal level in particular.
The problem then is to provide an integrated 3D MIM capacitor that does not have the aforementioned drawbacks.